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PSD3200 FAMILY
Flash Programmable System Device with 8032 Microcontroller Core
DATA BRIEFING
FEATURES SUMMARY s The PSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core The PSD3200 Family of Flash PSDs features dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and one External Interrupt. As with other Flash PSD families, the PSD3200 Family is also in-system programmable (ISP) via a JTAG ISP interface. Large 8 KByte SRAM with battery back-up option Dual bank Flash memories - 128 KByte or 256 KByte main Flash memory - 32 KByte secondary Flash memory
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Figure 1. Packages
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TQFP52 (T)
Content Security - Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories. High-speed clock standard 8032 core (12-cycle) USB Interface (PSD3234A-40U6 only) I2C interface for peripheral connections Five Pulse Width Modulator (PWM) channels Standalone Display Data Channel (DDC) Six I/O ports with up to 50 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage - 4.5 to 5.5 V - 3.0 to 3.6 V
TQFP80 (U)
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June 2002
Complete data available on Data-on-Disc CD-ROM or at www.st.com .
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SUMMARY DESCRIPTION s Dual bank Flash memories - Concurrent operation, read from memory one while erasing and writing the other. In-Application Programming (IAP) for remote updates - Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces - Large 32 KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation - Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks
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- One 16-bit PWM unit Standalone Display Data Channel (DDC) - For use in monitor, projector, and TV applications - Compliant with VESA standards DDC1 and DDC2B - Eliminate external DDC PROM Six I/O ports with up to 50 I/O pins - Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG - Eliminates need for external latches and logic
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3000 gate PLD with 16 macrocells - Create glue logic, state machines, delays, etc. - Eliminate external PALs, PLDs, and 74HCxx - Simple PSDsoft Express software ...Free
Large SRAM with battery back-up option - 8 KByte SRAM for RTOS, high-level languages, communication buffers, and stacks
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Programmable Decode PLD for flexible address mapping of all memories - Place individual Flash and SRAM sectors on any address boundary - Built-in page register breaks restrictive 8032 limit of 64 KByte address space - Special register swaps Flash memory segments between 8032 "program" space and "data" space for efficient In-Application Programming
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Supervisor functions - Generates reset upon low voltage or watchdog time-out. Eliminate external supervisor device - Reset In pin
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In-System Programming (ISP) via JTAG - Program entire chip in 10 - 25 seconds with no involvement of 8032 - Allows efficient manufacturing, easy product testing, and Just-In-Time inventory - Eliminate sockets and pre-programmed parts - Program with FlashLINKTM cable and any PC
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High-speed clock standard 8032 core (12-cycle) - 40 MHz operation at 5 V, 24 MHz at 3.3 V - Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts
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Content Security - Programmable Security Bit blocks access of device programmers and readers
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USB Interface (PSD3234A-40U6 only) - Supports USB 1.1 Slow Mode (1.5 Mbit/s) - Control endpoint 0 and interrupt endpoints 1 and 2
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Zero-Power Technology - Memories and PLD automatically reach standby current between input changes
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I2C interface for peripheral connections - Capable of master or slave operation Five Pulse Width Modulator (PWM) channels - Four 8-bit PWM units
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Packages - 52-pin TQFP - 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals
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PSD3200 FAMILY
Figure 2. PSD3200 Family Functional Modules
Port 3, UART, Intr, Timers,I2C
Port 1, Timers and 2nd UART and ADC
Port 4 PWM and DDC
Dedicated USB Pins
Port 3 8051 Core 2 UARTS Interrupt
Port 1 I2C 3 Timer / Counters 256 Byte SRAM 4 Channel ADC USB DDC PWM Reset Logic w/ 256 Byte & 5 Channels LVD & WDT SRAM Transceiver
MCU MODULE 8032 Internal Bus A0-A15 RD,PSEN WR,ALE PSD MODULE Page Register Decode PLD 1Mb or 2Mb Main Flash 256Kb Secondary Flash 64Kb SRAM Bus Interface D0-D7 Reset Port 0, 2 Ext. Bus
PSD Internal Bus
JTAG ISP
CPLD - 16 MACROCELLS
VCC, GND, XTAL
Port C, JTAG, PLD I/O and GPIO
Port A & B, PLD I/O and GPIO
Port D GPIO
Dedicated Pins
AI06619
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PSD3200 FAMILY
Table 1. 80-Pin Package Pin Description
Function Signal Name AD7-AD0 A11-A8 RxD2-RxD1 TxD2-TxD1 INT1-INT0 T2-T0 SDA1-SDA2 SCL1-SCL2 VSYNC T2EX ADC3-ADC0 PWM4-PWM0 USB-, USB+ AVREF RD_ WR_ PSEN_ ALE RESET_ XTAL1 XTAL2 In/Out Basic I/O I/O I/O I/O I/O I/O I/O General I/O port pins I/O I/O I/O I/O I/O I/O O O O O O I I O USB I/O Reference Voltage input for ADC Read signal, external bus Write signal, external bus PSEN signal, external bus Address Latch signal, external bus Active low reset input Oscillator input pin for system clock Oscillator output pin for system clock 1. 2. 3. 4. PLD Macro-cell outputs PLD inputs Latched Address Out (A0-A7) Peripheral I/O mode I2C Bus clock I/O VSYNC input for DDC interface Timer 2 Trigger input ADC Channels input 8-bit Pulse Width Modulation outputs Multiplexed Address/Data bus External Address Bus UART Receive UART Transmit Interrupt inputs / timer gate controls Counter inputs I2C Bus serial data I/O / DDC interface Alternate
PA7-PA0
I/O
General I/O port pins
PB7-PB0
I/O
General I/O port pins
1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) 1. PLD Macro-cell outputs 2. PLD inputs 3. SRAM stand by voltage input (VSTBY) 4. JTAG Interface (TDI, TDO, TMS, TCK, TSTAT, TERR) 5. SRAM battery-on indicator (PC4) 1. PLD I/O 2. Clock input to PLD and APD 3. Chip select to PSD Module
PC7-PC0
I/O
General I/O port pins
PD2-PD1
I/O
General I/O port pin
Note: PSD Port A and MCU Address/Data bus are added for 80-pin device
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PSD3200 FAMILY
Figure 3. TQFP52 Connections
44 RST-IN
PD1 1 PC7 2 PC6 3 PC5 4 PU 5 PC4 6 NC 7 VCC 8 GND 9 PC3 10 PC2 11 PC1 12 PC0 13
40 ADC2
41 ADC3
46 VREF
45 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5
43 PB6
42 PB7
39 P1.5 / ADC1 38 P1.4 / ADC0 37 P1.3 / TXD1 36 P1.2 / RXD1 35 P1.1 / T2X 34 P1.0 / T2 33 VCC 32 XTAL2 31 XTAL1 30 P3.7 / SCL1 29 P3.6 / SDA1 28 P3.5 / T1 27 P3.4 / T0
P4.7 / PWM4 14
P4.6 / PWM3 15
P4.5 / PWM2 16
P4.4 / PWM1 17
P4.3 / PWM0 18
GND 19
P4.2 / DDC VSYNC 20
P4.1 / DDC SCL 21
P4.0 / DDC SDA 22
P3.0 / RXD 23
P3.1 / TXD 24
P3.2 / EXINT0 25
P3.3 / EXINT1 26
AI05790B
Note: NC = Not Connected PU = Pull-up resistor required (2k for 3V devices, 7.5k for 5V devices)
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Figure 4. TQFP80 Connections
63 PSEN, CNTL2 79 P3.2 / EXINT0 61 P1.6 / ADC2 64 P1.7 / ADC3 62 WR, CNTL0 65 RD, CNTL1 75 P3.0 / RXD 77 P3.1 / TXD 68 RESET-IN
70 VREF
69 GND
80 PB0
78 PB1
76 PB2
74 PB3
73 PB4
72 PB5
67 PB6
PD2 1 P3.3 /EXINT1 2 PD1 3 PD0, ALE 4 PC7 5 PC6 6 PC5 7 USB- 8 PC4 9 USB+ 10 NC 11 V CC 12 GND 13 PC3 14 PC2 15 PC1 16 NC 17 P4.7 / PWM4 18 P4.6 / PWM3 19 PC0 20
66 PB7
71 NC
60 P1.5 / ADC1 59 P1.4 / ADC0 58 P1.3 / TXD1 57 P2.3, A11 56 P1.2 / RXD1 55 P2.2, A10 54 P1.1 / T2X 53 P2.1, A9 52 P1.0 / T2 51 P2.0, A8 50 VCC 49 XTAL2 48 XTAL1 47 P0.7, AD7 46 P3.7 / SCL1 45 P0.6, AD6 44 P3.6 / SDA1 43 P0.5, AD5 42 P3.5 / T1 41 P0.4, AD4
P4.5 / PWM2 23
P4.4 / PWM1 25
P4.3 / PWM0 27
P4.2 / DCC VSYNC 30
P4.1 / DDC SCL 31
P4.0 / DDC SDA 33
AD0, P0.0 36
AD1, P0.1 37
AD2, P0.2 38
AD3, P0.3 39
P3.4 / T0 40
PA7 21
PA6 22
PA5 24
PA4 26
PA3 28
GND 29
PA2 32
PA1 34
PA0 35
AI05791
Note: 1. NC = Not Connected 2. USB- needs a pull-up resistor (see the description of the USB function)
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PSD3200 FAMILY
PART NUMBERING Table 2. Ordering Information Scheme
Example: Device Type uPSD = Microcontroller PSD Family 3 = 8032 core PLD Size 2 = 16 Macrocells 3 = 32 Macrocells SRAM Size 1 = 16 Kbit 3 = 64 Kbit 5 = 256 Kbit Main Flash Memory Size 3 = 1 Mbit 4 = 2 Mbit 5 = 4 Mbit IP Mix A = USB, I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) B = I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) Operating Voltage blank = V CC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed 24 = 24 MHz 40 = 40 MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 1 = 0 to 70 C (commercial) 6 = -40 to 85 C (industrial) Optio n T = Tape & Reel Packing uPSD 3 2 3 4 BV - 24 U 6 T
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
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PSD3200 FAMILY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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